The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. For instance, patterns can be formed from a photo resist layer by passing light energy through a mask (or reticle) having an arrangement to image the desired pattern onto the photo resist layer. As a result, the pattern is transferred to the photo resist layer. In areas where the photo resist is sufficiently exposed and after a development cycle, the photo resist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, etc.). Portions of the photo resist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer. The exposed portions of the underlying layer can then be etched (e.g., by using a chemical wet etch or a dry reactive ion etch (RIE)) such that the pattern formed from the photo resist layer is transferred to the underlying layer. Alternatively, the photo resist layer can be used to block dopant implantation into the protected portions of the underlying layer or to retard reaction of the protected portions of the underlying layer. Thereafter, the remaining portions of the photo resist layer can be removed.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. As a result, there is a corresponding need to increase the resolution capability of lithography systems. Various resolution enhancement techniques (RET) have been proposed to aid in the lithography process. For example, alternating phase shift masks and full phase shift masks have been employed. As another example, dipole illumination sources have been used.
In conjunction with these resolution enhancement techniques dual mask exposures have been used. An example dual mask exposure can involve exposing a photo resist layer with a first mask of a mask pair and then separately exposing the same photo resist layer with a second mask of the mask pair. Variations to this basic dual mask exposure technique exist and will be discussed in greater detail in subsequent sections.
Conventionally, integrated circuit fabrication involves exposing the wafer to multiple mask images. To achieve an acceptable overlay among the physical layers having patterns defined by these mask images, alignment of each mask within a given tolerance should be achieved. As is known in the art, overlay relates the lateral positioning between physical layers comprising an integrated circuit. If the layers are not properly aligned with each other, the performance of the devices of the integrated circuit can be compromised. In this situation, it is likely that the integrated circuit, if not the entire wafer (upon which multiple integrated circuits may be fabricated), may be unusable.
In conventional wafer processing mask image alignment is achieved by establishing a zero mark on the wafer. Typically, the zero mark is the first structure printed onto the wafer. The zero mark can be carefully optimized to provide a reference point to which each exposure (e.g., all mask images) are aligned. It is noted that some physical layers (e.g., a metal layer) may adversely impact the use of the zero mark for subsequent mask images and, in this situation, a new zero mark can be established on the wafer for use in aligning subsequent mask images.
Conventionally, each mask image of a dual mask exposure is aligned to the zero mark. In some situations, this method of mask image alignment does not result in satisfactory alignment between the first mask image and the second mask image of the dual mask exposure.
Accordingly, there exists a need in the art for techniques of improving alignment in dual mask exposures.